It is known that MOSFET integrated circuits perform better when their common substrate is maintained at a predetermined voltage level. This can be accomplished by connecting the substrate to an external bias source or alternatively by incorporating into the integrated circuit a substrate bias generating circuit which is capable of generating a bias on the substrate and for maintaining it within a preselected range. This latter approach to biasing the substrate of integrated circuits is preferable to the earlier use of external bias sources because it eliminates the need for additional outside power supplies and the need for additional electrical connections to the substrate. Thus, many such on-chip substrate bias generators have been proposed, such as for example, the one discussed in an article by H. Frantz et al entitled "MOSFET Substrate Bias-Voltage Generator", published in the IBM Technical Disclosure Bulletin, Vol. 11, No. 10, page 1219, in March, 1969. Other references discussing substrate bias generating circuits and structures include U.S. Pat. Nos. 3,794,862, 4,115,794, 4,336,466, 4,378,506, and 4,403,158, and the copending related U.S. patent application Ser. No. 546,224 referred to above.
A substrate bias generator typically uses an oscillator circuit to provide a waveform potential to a charge pumping circuit. A diagram illustrating a conventional prior art substrate bias generating circuit is shown in FIG. 1, which is described in some detail in a later section of the specification. The charge pumping circuit, as discussed herein, is defined to include a capacitor, a first diode means that is connected between a first capacitor node and the substrate and a second diode means that is connected between the same first capacitor node and a reference potential, such as the ground. During operation charge is pumped from the substrate through the first diode means to the first capacitor node in response to a negative transition of a periodic input signal coupled through the capacitor to this first node, and then from there the pumped charge passes through the second diode means to the reference potential in response to a positive going transition of a periodic input signal. The typical diode means used in such applications are PN junction diodes or FET type diodes. For example, for N-channel MOS devices or for CMOS devices constructed on a P-type substrate, the substrate bias generator is used to apply a negative bias voltage to the substrate. It is therefore necessary to cause hole current to be drawn out of the substrate so as to drive the potential of the substrate to a negative level. The charge pumping efficiency of a charge pumping structure depends on the capacitance of the charging capacitor, the output voltage level of the oscillator which is applied on the capacitor, the pre-existing voltage level on the substrate and the threshold voltage of the diodes in the charge pumping circuit. Thus, for a given capacitor, a given oscillator output voltage, and a given substrate voltage level, the threshold voltage of the diodes used in the circuit will to a large extent determine the charge pumping efficiency of the circuit. The lower the threshold voltage level of the diodes the higher the charge pumping efficiency of the circuit. Furthermore, it is also important that the diode structures be designed so that they do not inject into the substrate majority or minority carriers during any portion of the pumping cycle. Among the limitations of many currently known charge pumping structures is their injection of charges into the substrate. This is undesirable regardless of the types of charge carriers injected. For example, the injections of electrons into a P-type substrate can cause the malfunction of active devices constructed in the substrate. However, even the injection of holes, which are the majority carriers in a P-type substrate, is undesirable because they are the very carriers which the charge pumping structure is pumping out of the substrate. Thus the injection of majority carriers is counterproductive to the efficient operation of the circuit as will be further discussed during the discussion of the prior art structure shown in FIG. 1.